1. Field of the Invention
The present invention relates to an output buffer circuit for digital signals and more particularly, to an output buffer circuit having a pair of p- and n-channel Metal-Oxide-Semiconductor Field-Effect Transistors (MOSFETs) in its output stage, which suppresses a peak current flowing through the pair of MOSFETs and operates at high switching rate.
2. Description of the Prior Art
Input and output buffer circuits have been popularly used in Very Large Scale Integrated circuits (VLSIs) for exchanging digital signals with respect to their outside circuitry.
An output buffer circuit receives a digital input signal and outputs a digital output signal for driving its external load, thereby setting the logic state of the external load at a logic low (L) level or a logic high (H) level according to the logic state of the applied input signal. When the output signals of a plurality of output buffer circuits in a VLSI are simultaneously switched to the same logic level L or H, the magnitude of the power supply current flowing through the VLSI changes largely and rapidly, resulting in noise in the VLSI due to the transient phenomena of the currents and/or voltages. This noise tends to cause malfunction of other circuits connected to the same power supply as that of the output buffer circuit, such as input buffer circuits. Therefore, to prevent this malfunction problem from occurring, a solution that the slew rate (i.e., the maximum rate of change with respect to an applied square or stepped wave) of the output signal of the output buffer circuit is suitably adjusted has been developed and practically used.
On the other hand, it is needless to say that output buffer circuits of this sort are required to operate or switched as fast as possible.
An example of prior-art output buffer circuits of this sort is disclosed in the Japanese Non-Examined Patent Publication No. 9-148909 published in June 1997, in which the control voltages applied to the gates of MOSFETs located in the output stage are adjusted to change rapidly and then, to change slowly at each switching operation of the MOSFETs.
FIG. 1 shows the circuit configuration of the prior-art output buffer circuit disclosed in the Japanese Non-Examined Patent Publication No. 9-148909.
As shown in FIG. 1, this prior-art output buffer circuit is comprised of p- and n-channel output MOSFETs M130 and M140, first and second threshold detection circuits T131, and T132, first and second switches S101 and S102, first and second resistors R131 and R141, p- and n-channel MOSFETs M131 and M132 forming a first Complementary MOS (CMOS) inverter, p- and n-channel MOSFETs M141 and M142 forming a second CMOS inverter, and input and output terminals 102 and 103. A digital input signal D.sub.IN is applied to the input terminal 102 and a digital output signal D.sub.OUT having the same logic state as that of the input signal D.sub.IN is derived from the output terminal 103. The reference symbol V.sub.CC denotes a power supply voltage.
The first and second CMOS inverters formed by the MOSFETs M131, M132, M141, and M142 constitute a previous stage 101 for inverting the input signal D.sub.IN and outputting an inverted one of the input signal D.sub.IN. The p- and n-channel output MOSFETs M130 and M140 constitute a CMOS output stage 104 for inverting the inverted signal from the previous stage 101 and outputting the digital output signal D.sub.OUT having the same logic state as that of the input signal D.sub.IN.
The first resistor R131, the first switch circuit S101, and the first threshold detection circuit T131 constitute a first slew-rate control circuit for controlling the changing rate of the gate voltage V.sub.G130 of the p-channel MOSFET M130 in the output stage 104. The first resistor R131 suppresses the rate of falling behavior from the logic H state to the logic L state of the gate voltage V.sub.G130 (i.e., the pull-down operation of the MOSFET M130). The first switch S101 forms a bypass of the first resistor R131, which is turned on or off under the control of the first threshold detection circuit T131. The first threshold detection circuit T131 detects whether the gate voltage V.sub.G130 of the p-channel MOSFET M130 is equal to or lower than the threshold voltage V.sub.THP at which the MOSFET M130 is switched from the OFF state to the ON state. Thus, when the gate voltage V.sub.G130 of the p-channel MOSFET M130 is equal to or lower than the threshold voltage V.sub.THP, the first threshold detection circuit T131 turns the first switch S101 off. When the gate voltage V.sub.G130 of the p-channel MOSFET M130 is higher than the threshold voltage V.sub.THP, the first threshold detection circuit T131 turns the first switch S101 on.
The second resistor R141, the second switch circuit S102, and the second threshold detection circuit T141 constitute a second slew-rate control circuit for controlling the changing rate of the gate voltage V.sub.G140 of the n-channel MOSFET M140 in the output stage 104. The second resistor R141 suppresses the rate of rising behavior from the logic L state to the logic H state of the gate voltage V.sub.G140 (i.e., the pull-up operation of the MOSFET M140). The second switch S102 forms a bypass of the second resistor R141, which is turned on or off under the control of the second threshold detection circuit T141. The second threshold detection circuit T141 detects whether the gate voltage V.sub.G140 of the n-channel MOSFET M140 is equal to or higher than the threshold voltage V.sub.THN at which the MOSFET M140 is switched from the OFF state to the ON state. Thus, when the gate voltage V.sub.G140 of the n-channel MOSFET M140 is equal to or higher than the threshold voltage V.sub.THN, the second threshold detection circuit T141 turns the second switch S102 off. When the gate voltage V.sub.G140 of the n-channel MOSFET M140 is lower than the threshold voltage V.sub.THN, the second threshold detection circuit T141 turns the second switch S102 on.
The prior-art output buffer circuit shown in FIG. 1 operates in the following way:
When the input signal D.sub.IN applied to the input terminal 102 is changed from the logic L state to the logic H state, the gate voltages V.sub.G130 and V.sub.G140 of the MOSFETs M130 and M140 in the output stage 104 are pulled down by the first and second CMOS inverters formed by the MOSFETs M131 and M132 and M141 and M142 in the previous stage 101, respectively. In this case, the p-channel MOSFET M130 is switched from the OFF state to the ON state, because the decreased (i.e., pulled-down) gate voltage V.sub.G130 of the MOSFET M130 becomes lower than its threshold voltage V.sub.THP. During this switching operation of the MOSFET M130, the first switch S101 is switched from the ON state to the OFF state by the first threshold detection circuit T131 at the time when the gate voltage V.sub.G130 of the MOSFET M130 is lowered to be equal to the threshold voltage V.sub.THP, thereby inserting the first resistor R131 into the path connecting the drains of the MOSFETs M131 and M132 of the first CMOS inverter. Thus, the decreasing rate of the threshold voltage V.sub.THP is suppressed.
As a result, when the input signal D.sub.IN is changed from the logic L state to the logic H state, the decreasing rate of the gate voltage V.sub.G130 of the MOSFET M130 is relatively higher until the gate voltage V.sub.G130 is lowered to be equal to the threshold voltage V.sub.THP, and is relatively lower after the gate voltage V.sub.G130 is lower than the threshold voltage V.sub.THP.
On the other hand, the n-channel MOSFET M140 in the output stage 104 is switched from the ON state to the OFF state, because the decreased (i.e., pulled-down) gate voltage V.sub.G140 of the MOSFET M140 becomes lower than its threshold voltage V.sub.THN. During this switching operation, the second switch S102 is kept in the ON state and accordingly, the drains of the MOSFETs M141 and M142 of the second CMOS inverter are directly connected to each other through the second switch S102. Thus, the decreasing rate of the threshold voltage V.sub.THN is not suppressed.
As a result, when the input signal D.sub.IN is changed from the logic L state to the logic H state, the decreasing rate of the gate voltage V.sub.G140 of the MOSFET M140 is kept high.
Because of the above-explained reason, the rising delay time of the output signal D.sub.OUT, which is defined as a delay from the time at which the input signal D.sub.IN is switched from the logic L state to the logic H state to the time at which the output signal D.sub.OUT begins to rise, can be shortened. Also, the rising slew-rate of the output signal D.sub.OUT can be suppressed.
Next, when the input signal D.sub.IN is changed from the logic H state to the logic L state, the gate voltages V.sub.G130 and V.sub.G140 of the MOSFETs M130 and M140 in the output stage 104 are pulled up by the first and second CMOS inverters in the previous stage 101, respectively. In this case, the n-channel MOSFET M140 is switched from the OFF state to be ON state because the increased (i.e., pulled-up) gate voltage V.sub.G140 of the MOSFET M140 becomes higher than its threshold voltage V.sub.THN. At this time, the second switch S102 is switched from the ON state to the OFF state when the gate voltage V.sub.G140 of the MOSFET M140 is raised to be equal to the threshold voltage V.sub.THN due to the operation of the second threshold detection circuit T141, thereby inserting the second resistor R141 into the path connecting the drains of the MOSFETs M141 and M142 of the second CMOS inverter. Thus, the increasing rate of the threshold voltage V.sub.THN is suppressed.
As a result, when the input signal D.sub.IN is changed from the logic H state to the logic L state, the changing rate of the gate voltage V.sub.G140 of the MOSFET M140 is relatively higher until the gate voltage V.sub.G140 is raised to be equal to the threshold voltage V.sub.THN, and is relatively lower after the gate voltage V.sub.G140 is higher than the threshold voltage V.sub.THN.
On the other hand, the p-channel MOSFET M130 in the output stage 104 is switched from the ON state to the OFF state because the increased (i.e., pulled-up) gate voltage V.sub.G130 of the MOSFET M130 becomes higher than its threshold voltage V.sub.THP. During this switching operation, the first switch S101 is kept in the ON state and accordingly, the drains of the MOSFETs M131 and M132 of the first CMOS inverter are directly connected to each other through the fist switch S101. Thus, the increasing rate of the threshold voltage V.sub.THP is not suppressed.
As a result, when the input signal D.sub.IN is changed from the logic H state to the logic L state, the changing rate of the gate voltage V.sub.G130 of the MOSFET M130 is kept high.
Because of the above-explained reason, the falling delay time of the output signal D.sub.OUT, which is defined as a delay from the time at which the input signal D.sub.IN is switched from the logic H state to the logic L state to the time at which the output signal D.sub.OUT begins to fall, can be shortened. Also, the falling slew-rate of the output signal D.sub.OUT can be suppressed.
As described above, the rising and falling slew-rates of the output signal D.sub.OUT can be shortened while suppressing the rapid change of the power supply current. This prevents the malfunction of the VLSI including the prior-art output buffer circuit shown in FIG. 1.
With the prior-art output buffer circuit disclosed in the Japanese Non-Examined Patent Publication No. 9-148909, which is shown in FIG. 1, when the input signal D.sub.IN is changed from the logic L state to the logic H state, the changing rate of the gate voltage V.sub.G130 of the MOSFET M130 is relatively higher until the gate voltage V.sub.G130 is lowered to be equal to the threshold voltage V.sub.THP. However, it is lowered after the gate voltage V.sub.G130 is lower than the threshold voltage V.sub.THP. On the other hand, when the input signal D.sub.IN is changed from the logic H state to the logic L state, the changing rate of the gate voltage V.sub.G140 of the MOSFET M140 is relatively higher until the gate voltage V.sub.G140 is raised to be equal to the threshold voltage V.sub.THN. However, it is lowered after the gate voltage V.sub.G140 is higher than the threshold voltage V.sub.THN. Therefore, there is a problem that the effect to decrease the delay time of the change of the output signal D.sub.OUT with respect to the change of the input signal D.sub.IN is insufficient.
Moreover, the gate voltage V.sub.G130 of the MOSFET M130 varies even after it is lowered to the threshold voltage V.sub.THP and the gate voltage V.sub.G140 of the MOSFET M140 varies even after the gate voltage V.sub.G140 is raised to the threshold voltage V.sub.THN. Therefore, there is another problem that the peak current flowing through the MOSFETs M130 and M140 in the output stage 104 cannot be satisfactorily decreased.
Another example of the prior-art output buffer circuits of the sort is disclosed in the Japanese Non-Examined Patent Publication No. 9-93111 published in April 1997.
The prior-art output buffer circuit disclosed in the Japanese Non-Examined Patent Publication No. 9-93111 is comprised of a p-channel MOSFET and an n-channel MOSFET located in an output stage, and first and second slew-rate circuits located in a previous stage to the output stage.
The source and drain of the p-channel MOSFET in the output stage are connected to the power supply node applied with a power supply voltage V.sub.CC and the output node. The source and drain of the n-channel MOSFET in the output stage are connected to the output node and the ground node. Therefore, the connection of these two MOSFETs is the same as that of the MOSFETs M130 and M140 shown in FIG. 1.
The first slew-rate circuit includes MOSFETs that are switched by a digital input signal applied to the prior-art output buffer circuit and by a digital feedback signal fed-back from the output stage. The first slew-rate circuit has an input-output characteristic that the output changing rate at the time when the input signal is switched from the logic L state to the logic H state is higher than that at the time when the input signal is switched from the logic H state to the logic L state. The output of the first slew-rate circuit is applied to the gate of the n-channel MOSFET in the output stage, thereby controlling the gate voltage of this n-channel MOSFET.
Similarly, the second slew-rate circuit includes MOSFETs that are switched by the digital input signal applied into the prior-art output buffer circuit and by the digital feedback signal fed-back from the output stage. The second slew-rate circuit has an input-output characteristic that the output changing rate at the time when the input signal is switched from the logic L state to the logic H state is lower than that at the time when the input signal is switched from the logic H state to the logic L state. The output of the second slew-rate circuit is applied to the gate of the p-channel MOSFET in the output stage, thereby controlling the gate voltage of this p-channel MOSFET.
Thus, due to the input-output characteristics of the first and second slew-rate circuits, the gate voltages of the n- and p-channel MOSFETs in the output stage can be raised from the ground level to the intermediate level of (V.sub.CC /2) at a relatively higher rate and then, it can be raised from the intermediate level of V.sub.CC /2) to the highest level of V.sub.CC at a relatively lower rate. Similarly, the gate voltages of the p- and n-channel MOSFETs in the output stage can be lowered from the highest level of V.sub.CC to the intermediate level of (V.sub.CC /2) at a relatively higher rate and then, it can be lowered from the intermediate level of (V.sub.CC /2) to the ground level at a relatively lower rate. Accordingly, the delay of change of the output signal with respect to that of the input signal can be suppressed and at the same time, the peak value of the output current can be lowered.
Also, because the MOSFETs in the first and second slew-rate circuits are switched by using the digital feedback signal (i.e., the input signal) from the output stage, the characteristic fluctuation of the prior-art output buffer circuit due to the threshold voltage fluctuation occurring in the fabrication processes can be suppressed.
With the prior-art output buffer circuit disclosed in the Japanese Non-Examined Patent Publication No. 9-93111, however, due to the input-output characteristic of the first slew-rate circuit, the gate voltages of the n- and p-channel MOSFETs in the output stage are further raised to the highest level of V.sub.CC at a relatively lower rate even after they become equal to the intermediate level of (V.sub.CC /2). Also, they are further lowered to the ground level at a relatively lower rate even after they become equal to the intermediate level of (V.sub.CC /2). Therefore, there is a problem that the peak current flowing through the MOSFETs in the output stage cannot be satisfactorily decreased.
Moreover, since a time delay of the output signal occurs when the changing rate of the gate voltages of the n- and p-channel MOSFETs in the output stage is switched, there is another problem that the effect to decrease the delay time of the change of the output signal with respect to the change of the input signal is insufficient.